1. Field of the Invention
The present invention relates to a substrate having a built-in semiconductor apparatus and a manufacturing method thereof.
This application is counterpart of Japanese patent application, Ser. No. 336380/2003, filed Sep. 26, 2003, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
There has been proposed a substrate having a built-in semiconductor chip to which an active element such as a transistor is formed or a substrate having a built-in passive element such as a capacitor or a resistor with a demand for high-density packaging of an electronic device (see, e.g., patent document1).
(Patent Document 1) Japanese patent application laid-open No. 2002-170827
However, a substrate having, e.g., a built-in semiconductor chip has the following problems.
First, in a bare chip state, it is hard to guarantee KGD (Known Good Die: quality assurance chip), i.e., a perfect non-defective unit. As a result, a semiconductor chip which is a defective unit is built in a substrate with a fixed probability. Therefore, in case of an integrated substrate having many built-in semiconductor chips, a further reduction in yield ratio occurs. Furthermore, since burn-in, i.e., a pre-use operation in order to find a defect cannot be carried out before building such chips in the substrate, there is known that an initial percent defective of the integrated substrate is high.
Second, when a pitch (or an interval) between pads provided to a semiconductor chip is narrow, many build-up layers are required when building such a chip in a substrate. Therefore, a product cost per integrated substrate is high, and pulling wirings from pads with a narrow pitch interval to an external terminal on the surface of the integrated substrate becomes complicated. Therefore, there is fear of a reduction in yield ratio.
Thus, there has been recently proposed a new method to build a WCSP (Wafer level Chip Size Package) which is guaranteed as a perfect non-defective unit in a packaging state into a substrate. The WCSP is a package which is obtained by forming an individual piece after performing packaging in a wafer state and has an outside dimension which is substantially equal to a chip size. In the WCSP, a pitch between external terminals can be expanded by a wiring layer,(which is also referred to as a redistribution wiring layer) capable of rearranging a position of an external terminal, thereby easing the difficulty in pulling the wirings to the external terminal on the surface of the integrated substrate.
However, with a demand for realization of multi-pin of the WCSP involved by high integration in recent years, many build-up layers are naturally required when a pitch between external terminals must be further narrowed. Therefore, a product cost in an integrated substrate unit is increased, and there is fear of a reduction in yield ratio due to complexity of pulling wirings from pads with a narrow pitch interval to external terminals on the surface of the integrated substrate. It is to be noted that, in 2002, the WCSP having a wiring pitch not more than 25 μm is mass-produced and, on the other hand, a wiring pitch of a build-up substrate is 50 μm and a wiring pitch of a multilayer wiring substrate is 70 μm (Actual Packaging Technology Road Map (JEITA), 2001). It can be understood from this fact that narrowing the wiring pitch in the WCSP rapidly advances.